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CDP1802A, CDP1802AC,
CDP1802BC
CMOS 8-Bit Microprocessors
Features
Description
• Maximum Input Clock Maximum Frequency Options
The CDP1802 family of CMOS microprocessors are 8-bit At VDD = 5V
register oriented central processing units (CPUs) designed - CDP1802A, AC . . . . . . . . . . . . . . . . . . . . . . . . . 3.2MHz
for use as general purpose computing or control elements in - CDP1802BC. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0MHz
a wide range of stored program systems or products.
• Maximum Input Clock Maximum Frequency Options
The CDP1802 types include all of the circuits required for At VDD = 10V
fetching, interpreting, and executing instructions which have - CDP1802A, AC . . . . . . . . . . . . . . . . . . . . . . . . . 6.4MHz
been stored in standard types of memories. Extensive • Minimum Instruction Fetch
input/output (I/O) control features are also provided to facili- -Execute Times
- CDP1802A, AC . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0µs
The 1800 series architecture is designed with emphasis on - CDP1802BC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2µs
the total microcomputer system as an integral entity so thatsystems having maximum flexibility and minimum cost can • Any Combination of Standard RAM and ROM Up to
be realized. The 1800 series CPU also provides a synchro- 65,536 Bytes
nous interface to memories and external controllers for I/O • 8-Bit Parallel Organization With Bidirectional Data Bus
devices, and minimizes the cost of interface controllers. Fur- and Multiplexed Address Bus
ther, the I/O interface is capable of supporting devices oper-ating in polled, interrupt driven, or direct memory access • 16 x 16 Matrix of Registers for Use as Multiple
Program Counters, Data Pointers, or Data Registers
The CDP1802A and CDP1802AC have a maximum input • On-Chip DMA, Interrupt, and Flag Inputs
clock frequency of 3.2MHz at VDD = 5V. The CDP1802A and • Programmable Single
CDP1802AC are functionally identical. They differ in that the -Bit Output Port
CDP1802A has a recommended operating voltage range of • 91 Easy-to-Use Instructions
4V to 10.5V, and the CDP1802AC a recommended operat- The CDP1802BC is a higher speed version of the CDP1802AC, having a maximum input clock frequency of 5.0MHz at VDD = 5V, and a recommended operating voltage Ordering Information
PART NUMBER
5V - 3.2MHz
TEMPERATURE RANGE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright Intersil Corporation 19993-3 CDP1802A, CDP1802AC, CDP1802BC
40 LEAD PDIP (PACKAGE SUFFIX E)
44 LEAD PLCC
40 LEAD SBDIP (PACKAGE SUFFIX D)
(PACKAGE TYPE Q)
INTERRUPT
1 44 43 42 41 40
18 19 20 21 22 23 24 25 26 27 28
ADDRESS BUS
INPUT PORT CS2
8-BIT CPU
32 BYTE RAM
FIGURE 1. TYPICAL CDP1802 SMALL MICROPROCESSOR SYSTEM
CDP1802A, CDP1802AC, CDP1802BC
Block Diagram
I/O REQUESTS
MEMORY ADDRESS LINES
I/O FLAGS
MA6 MA4 MA2 MA0 EF1
MA7 MA5 MA3 MA1
CONTROL AND
TIMING LOGIC
TO INSTRUCTION
REGISTER
R(0).1 R(0).0
R(1).1 R(1).0 R
R(2).1 R(2).0
R(9).1 R(9).0
R(A).1 R(A).0
COMMANDS
R(E).1 R(E).0
R(F).1 R(F).0
8-BIT BIDIRECTIONAL DATA BUS
FIGURE 2.
CDP1802A, CDP1802AC, CDP1802BC
Absolute Maximum Ratings
Thermal Information
(All Voltages Referenced to VSS Terminal) PDIP . . . . . . . . . . . . . . . . . . . . . . . . . .
CDP1802A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V PLCC . . . . . . . . . . . . . . . . . . . . . . . . . .
CDP1802AC, CDP1802BC . . . . . . . . . . . . . . . . . . . . -0.5V to +7V SBDIP . . . . . . . . . . . . . . . . . . . . . . . . .
Input Voltage Range, All Inputs . . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, any One Input . . . . . . . . . . . . . . . . . . . . . . . . .±10mA TA = Full Package Temperature Range . . . . . . . . . . . . . . . 100mW Package Type D . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oCPackage Type E and Q . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC Storage Temperature Range (TSTG) . . . . . . . . . . . . -65oC to +150oCLead Temperature (During Soldering) At distance 1/16 ±1/32 In. (1.59 ± 0.79mm)from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oCLead Tips Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationof the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions TA = -40oC to +85oC. For maximum reliability, operating conditions should be selected so
that operation is always within the following ranges: TEST CONDITIONS
CDP1802A
CDP1802AC
CDP1802BC
PARAMETER
1. Printed circuit board mount: 57mm x 57mm minimum area x 1.6mm thick G10 epoxy glass, or equivalent.
2. VCC must never exceed VDD.
3. Equals 2 machine cycles - one Fetch and one Execute operation for all instructions except Long Branch and Long Skip, which require 3 machine cycles - one Fetch and two Execute operations.
4. θJA is measured with component mounted on an evaluation board in free air.
CDP1802A, CDP1802AC, CDP1802BC
Static Electrical Specifications at TA = -40oC to +85oC, Except as Noted
CDP1802AC,
TEST CONDITIONS
CDP1802A
CDP1802BC
PARAMETER
CDP1802A, CDP1802AC, CDP1802BC
Static Electrical Specifications at TA = -40oC to +85oC, Except as Noted (Continued)
CDP1802AC,
TEST CONDITIONS
CDP1802A
CDP1802BC
PARAMETER
1. Typical values are for TA = +25oC and nominal VDD.
2. Idle “00” at M(0000), CL = 50pF.
Dynamic Electrical Specifications T
CDP1802A,
CONDITIONS
CDP1802AC
CDP1802BC
PARAMETER
PROPAGATION DELAY TIMES
CDP1802A, CDP1802AC, CDP1802BC
Dynamic Electrical Specifications T
5%, Except as Noted (Continued)
CDP1802A,
CONDITIONS
CDP1802AC
CDP1802BC
PARAMETER
MINIMUM SET UP AND HOLD TIMES
CDP1802A, CDP1802AC, CDP1802BC
Dynamic Electrical Specifications T
5%, Except as Noted (Continued)
CDP1802A,
CONDITIONS
CDP1802AC
CDP1802BC
PARAMETER
1. Typical values are for TA = +25oC and nominal VDD.
2. Maximum limits of minimum characteristics are the values above which all devices function.
Timing Specifications as a function of T(T = 1/fCLOCK) at TA = -40 to +85oC, Except as Noted
CDP1802A,
TEST CONDITIONS
CDP1802AC
CDP1802BC
PARAMETERS
CDP1802A, CDP1802AC, CDP1802BC
Timing Specifications as a function of T(T = 1/fCLOCK) at TA = -40 to +85oC, Except as Noted
CDP1802A,
TEST CONDITIONS
CDP1802AC
CDP1802BC
PARAMETERS
1. Typical values are for TA = +25oC and nominal VDD.
Timing Waveforms
FETCH (READ)
EXECUTE (WRITE)
00 01 10 11 20 21 30 31 40 41 50 51 60 61 70 71 00 01 10 11 20 21 30 31 40 41 50 51 60 61 70 71 00
VALID INPUT DATA
VALID OUTPUT DATA
FIGURE 3. BASIC DC TIMING WAVEFORM, ONE INSTRUCTION CYCLE
CDP1802A, CDP1802AC, CDP1802BC
Timing Waveforms (Continued)
tPLH, tPHL
HIGH ORDER
tPLH, tPHL
LOW ORDER
PLH, tPHL
ADDRESS BYTE
ADDRESS BYTE
READ CYCLE)
WRITE CYCLE)
DATA FROM
tPLH, tPHL
CPU TO BUS
tPLH, tPHL
tPLH, tPHL
N0, N1, N2
(I/O EXECUTION
DATA
LATCHED IN CPU
DATA FROM
BUS TO CPU
DMA SAMPLED (S1, S2, S3)
INTERRUPT
SAMPLED (S1, S2)
INTERRUPT
FLAG LINES
SAMPLED (IN S1)
ANY NEGATIVE
TRANSITION
1. This timing diagram is used to show signal relationships only and does not represent any specific machine cycle.
2. All measurements are referenced to 50% point of the waveforms.
3. Shaded areas indicate “Don’t Care” or undefined state. Multiple transitions may occur during this period.
FIGURE 4. TIMING WAVEFORM
CDP1802A, CDP1802AC, CDP1802BC
Machine Cycle Timing Waveforms (Propagation Delays Not Shown)
CYCLE (n + 1)
CYCLE (n + 2)
LOW ADDRESS
LOW ADDRESS
LOW ADDRESS
FIGURE 5. GENERAL TIMING WAVEFORMS
INSTRUCTION
FETCH (S0)
EXECUTE (S1)
FETCH (S0)
MEMORY READ CYCLE
NON MEMORY CYCLE
MEMORY READ CYCLE
MWR (HIGH)
VALID OUTPUT
ALLOWABLE MEMORY ACCESS
“DON’T CARE” OR INTERNAL DELAYS
HIGH IMPEDANCE STATE
FIGURE 6. NON-MEMORY CYCLE TIMING WAVEFORMS
INSTRUCTION
FETCH (S0)
EXECUTE (S1)
FETCH (S0)
MEMORY READ CYCLE
MEMORY WRITE CYCLE
MEMORY READ CYCLE
VALID OUTPUT
ALLOWABLE MEMORY ACCESS
CPU OUTPUT
VALID DATA
TO MEMORY
“DON’T CARE” OR INTERNAL DELAYS
HIGH IMPEDANCE STATE
FIGURE 7. MEMORY WRITE CYCLE TIMING WAVEFORMS
CDP1802A, CDP1802AC, CDP1802BC
Machine Cycle Timing Waveforms (Propagation Delays Not Shown) (Continued)
INSTRUCTION
FETCH (S0)
EXECUTE (S1)
FETCH (S0)
MEMORY READ CYCLE
MEMORY READ CYCLE
MEMORY READ CYCLE
MWR (HIGH)
ALLOWABLE MEMORY ACCESS
VALID OUTPUT
“DON’T CARE” OR INTERNAL DELAYS
HIGH IMPEDANCE STATE
FIGURE 8. MEMORY READ CYCLE TIMING WAVEFORMS
INSTRUCTION
FETCH (S0)
EXECUTE (S1)
EXECUTE (S1)
FETCH (S0)
MEMORY READ CYCLE
MEMORY READ CYCLE
MEMORY READ CYCLE
MWR (HIGH)
ALLOWABLE MEMORY ACCESS
VALID OUTPUT
VALID OUTPUT
VALID
OUTPUT
“DON’T CARE” OR INTERNAL DELAYS
HIGH IMPEDANCE STATE
FIGURE 9. LONG BRANCH OR LONG SKIP CYCLE TIMING WAVEFORMS
CDP1802A, CDP1802AC, CDP1802BC
Machine Cycle Timing Waveforms (Propagation Delays Not Shown) (Continued)
CYCLE (n + 1)
INSTRUCTION
FETCH (S0)
EXECUTE (S1)
VALID OUTPUT
ALLOWABLE MEMORY ACCESS
VALID DATA FROM INPUT DEVICE
MEMORY READ CYCLE
MEMORY WRITE CYCLE
“DON’T CARE” OR INTERNAL DELAYS
HIGH IMPEDANCE STATE
USER GENERATED SIGNAL
FIGURE 10. INPUT CYCLE TIMING WAVEFORMS
CYCLE (n + 1)
INSTRUCTION
FETCH (S0)
EXECUTE (S1)
ALLOWABLE MEMORY ACCESS
ALLOWABLE MEMORY ACCESS
VALID OUTPUT
VALID DATA FROM MEMORY
DATA STROBE
(MRD • TPB • N)
MEMORY READ CYCLE
MEMORY READ CYCLE
“DON’T CARE” OR INTERNAL DELAYS
HIGH IMPEDANCE STATE
USER GENERATED SIGNAL
FIGURE 11. OUTPUT CYCLE TIMING WAVEFORMS
CDP1802A, CDP1802AC, CDP1802BC
Machine Cycle Timing Waveforms (Propagation Delays Not Shown) (Continued)
CYCLE (n+1)
CYCLE (n+2)
INSTRUCTION
FETCH (S0)
EXECUTE (S1)
VALID OUTPUT
VALID DATA FROM INPUT DEVICE
MEMORY READ CYCLE
MEMORY READ, WRITE
MEMORY WRITE CYCLE
OR NON-MEMORY CYCLE
“DON’T CARE” OR INTERNAL DELAYS
HIGH IMPEDANCE STATE
USER GENERATED SIGNAL
FIGURE 12. DMA IN CYCLE TIMING WAVEFORMS
CYCLE (n + 1)
CYCLE (n + 2)
INSTRUCTION
FETCH (S0)
EXECUTE (S1)
VALID OUTPUT
VALID DATA FROM MEMORY
(S2 • TPB)
MEMORY READ CYCLE
MEMORY READ, WRITE
MEMORY READ CYCLE
OR NON-MEMORY CYCLE
“DON’T CARE” OR INTERNAL DELAYS
HIGH IMPEDANCE STATE
USER GENERATED SIGNAL
FIGURE 13. DMA OUT CYCLE TIMING WAVEFORMS
CDP1802A, CDP1802AC, CDP1802BC
Machine Cycle Timing Waveforms (Propagation Delays Not Shown) (Continued)
CYCLE (n + 1)
CYCLE (n + 2)
INSTRUCTION
FETCH (S0)
EXECUTE (S1)
INTERRUPT (S3)
INTERRUPT
(INTERNAL) IE
VALID OUTPUT
MEMORY READ, WRITE
MEMORY READ CYCLE
NON-MEMORY CYCLE
OR NON-MEMORY CYCLE
“DON’T CARE” OR INTERNAL DELAYS
HIGH IMPEDANCE STATE
USER GENERATED SIGNAL
FIGURE 14. INTERRUPT CYCLE TIMING WAVEFORMS
Performance Curves
L, LOAD CAPACITANCE = 50pF
L, LOAD CAPACITANCE = 50pF
VCC = VDD = 10V
VCC = 5V, VDD = 10V
VCC = VDD = 5V
UENCY (MHz)
UENCY (MHz)
CC = VDD = 5V
, SYSTEM MAXIMUM CLOCK
, SYSTEM MAXIMUM CLOCK
TA, AMBIENT TEMPERATURE (oC)
TA, AMBIENT TEMPERATURE (oC)
FIGURE 15. CDP1802A, AC TYPICAL MAXIMUM CLOCK
FIGURE 16. CDP1802BC TYPICAL MAXIMUM CLOCK
FREQUENCY AS A FUNCTION OF TEMPERATURE
FREQUENCY AS A FUNCTION OF TEMPERATURE
CDP1802A, CDP1802AC, CDP1802BC
Performance Curves (Continued)
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
VCC = VDD = 5V
VGS, GATE-TO-VOLTAGE = -5V
VCC = VDD = 10V
, TRANSITION TIME (ns)
VCC = VDD = 5V
VCC = VDD = 10V
, OUTPUT HIGH (SOURCE) CURRENT (mA)
TA, AMBIENT TEMPERATURE = -40oC TO +85oC
L, LOAD CAPACITANCE (pF)
FIGURE 17. TYPICAL TRANSITION TIME vs LOAD CAPACI-
FIGURE 18. CDP1802A, AC MINIMUM OUTPUT HIGH (SOURCE)
TANCE FOR ALL TYPES
CURRENT CHARACTERISTICS
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
TA = -40oC TO +85oC
VGS, GATE-TO-SOURCE = 10V
VGS, GATE-TO-VOLTAGE = -5V
W (SINK) CURRENT (mA)
, OUTPUT LO
, OUTPUT HIGH (SOURCE) CURRENT (mA)
DS, DRAIN-TO-SOURCE VOLTAGE (V)
FIGURE 19. CDP1802A, AC MINIMUM OUTPUT LOW (SINK)
FIGURE 20. CDP1802BC MINIMUM OUTPUT HIGH (SOURCE)
CURRENT CHARACTERISTICS
CURRENT CHARACTERISTICS
TA = -40oC TO +85oC
VCC = VDD = 5V
TION DELA
W (SINK) CURRENT (mA)
TIME (ns)
CC = VDD = 10V
VGS, GATE-TO-SOURCE = 5V
CC = VDD = 5V
VCC = VDD = 10V
, OUTPUT LO
L, ∆ LOAD CAPACITANCE (pF)
DS, DRAIN-TO-SOURCE VOLTAGE (V)
NOTE: ANY OUTPUT EXCEPT XTAL
FIGURE 21. CDP1802BC MINIMUM OUTPUT LOW (SINK)
FIGURE 22. TYPICAL CHANGE IN PROPAGATION DELAY AS A
CURRENT CHARACTERISTICS
FUNCTION OF A CHANGE IN LOAD CAPACITANCE
FOR ALL TYPES
CDP1802A, CDP1802AC, CDP1802BC
Performance Curves (Continued)
CC = VDD = 10V
WER DISSIP
10 BRANCH
FOR CDP1802D (mW)
, TYPICAL PO DP
VCC = VDD = 5V
fCL, CLOCK INPUT FREQUENCY (MHz)
NOTE: IDLE = “00” AT M(0000), BRANCH = “3707” AT M(8107), CL = 50pF FIGURE 23. TYPICAL POWER DISSIPATION AS A FUNCTION OF CLOCK FREQUENCY FOR BRANCH INSTRUCTION AND IDLE
INSTRUCTION FOR ALL TYPES
Signal Descriptions
Bus 0 to Bus 7 (Data Bus)
Interrupt Action - X and P are stored in T after executing
current instruction; designator X is set to 2; designator P is
8-bit bidirectional DATA BUS lines. These lines are used for set to 1; interrupt enable is reset to 0 (inhibit); and instruction transferring data between the memory, the microprocessor, execution is resumed. The interrupt action requires one N0 to N2 (I/O Control Lines)
DMA Action - Finish executing current instruction; R(0)
Activated by an I/O instruction to signal the I/O control logic of points to memory area for data transfer; data is loaded into a data transfer between memory and I/O interface. These or read out of memory; and increment R(0).
lines can be used to issue command codes or device selec- NOTE: In the event of concurrent DMA and Interrupt requests, tion codes to the I/O devices (independently or combined with DMA-lN has priority followed by DMA-OUT and then Interrupt.
the memory byte on the data bus when an I/O instruction isbeing executed). The N bits are low at all times except when SC0, SC1, (2 State Code Lines)
an I/O instruction is being executed. During this time their These outputs indicate that the CPU is: 1) fetching an state is the same as the corresponding bits in the N register.
instruction, or 2) executing an instruction, or 3) processing a The direction of data flow is defined in the I/O instruction by bit DMA request, or 4) acknowledging an interrupt request. The N3 (internally) and is indicated by the level of the MRD signal.
levels of state code are tabulated below. All states are validat TPA. H = VCC, L = VSS.
MRD = VCC: Data from I/O to CPU and Memory STATE CODE LINES
STATE TYPE
EF1 to EF4 (4 Flags)
These inputs enable the I/O controllers to transfer statusinformation to the processor. The levels can be tested by the conditional branch instructions. They can be used in con- junction with the INTERRUPT request line to establish inter-rupt priorities. These flags can also be used by I/O devices to “call the attention” of the processor, in which case the pro-gram must routinely test the status of these flag(s). The TPA, TPB (2 Timing Pulses)
flag(s) are sampled at the beginning of every S1 cycle.
Positive pulses that occur once in each machine cycle (TPB INTERRUPT, DMA-lN, DMA-OUT (3 I/O Requests)
follows TPA). They are used by I/O controllers to interpretcodes and to time interaction with the data bus. The trailing These inputs are sampled by the CPU during the interval edge of TPA is used by the memory system to latch the between the leading edge of TPB and the leading edge of higher-order byte of the 16-bit memory address. TPA is sup- pressed in IDLE when the CPU is in the load mode.
CDP1802A, CDP1802AC, CDP1802BC
MA0 to MA7 (8 Memory Address Lines)
Architecture
In each cycle, the higher-order byte of a 16-bit CPU memory The CPU block diagram is shown in Figure 2. The principal address appears on the memory address lines MA0-7 first.
feature of this system is a register array (R) consisting of six- Those bits required by the memory system can be strobed teen 16-bit scratchpad registers. Individual registers in the into external address latches by timing pulse TPA. The low array (R) are designated (selected) by a 4-bit binary code order byte of the 16-bit address appears on the address lines from one of the 4-bit registers labeled N, P and X. The con- after the termination of TPA. Latching of all 8 higher-order tents of any register can be directed to any one of the follow- address bits would permit a memory system of 64K bytes.
MWR (Write Pulse)
1. The external memory (multiplexed, higher-order byte first, A negative pulse appearing in a memory-write cycle, afterthe address lines have stabilized.
2. The D register (either of the two bytes can be gated to D).
MRD (Read Level)
3. The increment/decrement circuit where it is increased or decreased by one and stored back in the selected 16-bit A low level on MRD indicates a memory read cycle. It can be used to control three-state outputs from the addressed mem-ory which may have a common data input and output bus. If a The three paths, depending on the nature of the instruction, memory does not have a three-state high-impedance output, may operate independently or in various combinations in the MRD is useful for driving memory/bus separator gates. It is also used to indicate the direction of data transfer during an With two exceptions, CPU instruction consists of two 8- I/O instruction. For additional information see Table 1.
clock-pulse machine cycles. The first cycle is the fetch cycle,and the second - and third if necessary - are execute cycles.
During the fetch cycle the four bits in the P designator select Single bit output from the CPU which can be set or reset one of the 16 registers R(P) as the current program counter.
under program control. During SEQ or REQ instruction exe- The selected register R(P) contains the address of the mem- cution, Q is set or reset between the trailing edge of TPA and ory location from which the instruction is to be fetched.
When the instruction is read out from the memory, the higherorder 4 bits of the instruction byte are loaded into the register and the lower order 4 bits into the N register. The content ofthe program counter is automatically incremented by one so Input for externally generated single-phase clock. The clock is that R(P) is now “pointing” to the next byte in the memory.
counted down internally to 8 clock pulses per machine cycle.
The X designator selects one of the 16 registers R(X) to “point” to the memory for an operand (or data) in certain ALU Connection to be used with clock input terminal, for an exter- nal crystal, if the on-chip oscillator is utilized. The crystal is The N designator can perform the following five functions connected between terminals 1 and 39 (CLOCK and XTAL) depending on the type of instruction fetched: in parallel with a resistance (10MΩ typ). Frequency trimmingcapacitors may be required at terminals 1 and 39. For addi- 1. Designate one of the 16 registers in R to be acted upon tional information, see Application Note AN6565.
2. Indicate to the I/O devices a command code or device WAIT, CLEAR (2 Control Lines)
Provide four control modes as listed in the following truth table: 3. Indicate the specific operation to be executed during the ALU instructions, types of test to be performed during the Branch instruction, or the specific operation required in a class of miscellaneous instructions (70 - 73 and 78 - 7B).
4. Indicate the value to be loaded into P to designate a new register to be used as the program counter R(P).
5. Indicate the value to be loaded into X to designate a new register to be used as data pointer R(X).
VDD, VSS, VCC (Power Levels)
The registers in R can be assigned by a programmer in three different ways: as program counters, as data pointers, or as scratchpad locations (data registers) to hold two bytes of data.
operate at maximum speed while interfacing with peripheral Program Counters
devices operating at lower voltage. VCC must be less than orequal to VDD. All outputs swing from VSS to VCC. The recom- Any register can be the main program counter; the address mended input voltage swing is VSS to VCC.
of the selected register is held in the P designator. Other reg- CDP1802A, CDP1802AC, CDP1802BC
isters in R can be used as subroutine program counters. By Interrupt Servicing
single instruction the contents of the P register can be Register R(1) is always used as the program counter when- changed to effect a “call” to a subroutine. When interrupts ever interrupt servicing is initiated. When an interrupt are being serviced, register R(1) is used as the program request occurs and the interrupt is allowed by the program counter for the user's interrupt servicing routine. After reset, (again, nothing takes place until the completion of the cur- and during a DMA operation, R(0) is used as the program rent instruction), the contents of the X and P registers are counter. At all other times the register designated as pro- stored in the temporary register T, and X and P are set to gram counter is at the discretion of the user.
new values; hex digit 2 in X and hex digit 1 in P. Interrupt Data Pointers
Enable is automatically deactivated to inhibit further inter-rupts. The user's interrupt routine is now in control; the con- The registers in R may be used as data pointers to indicate a tents of T may be saved by means of a single instruction (78) location in memory. The register designated by X (i.e., R(X)) in the memory location pointed to by R(X). At the conclusion points to memory for the following instructions (see Table 1).
of the interrupt, the user's routine may restore the pre-inter- 1. ALU operations F1 - F5, F7, 74, 75, 77 rupted value of X and P with a single instruction (70 or 71).
The Interrupt Enable flip-flop can be activated to permit fur- ther interrupts or can be disabled to prevent them.
CPU Register Summary
4. Certain miscellaneous instructions - 70 - 73, 78, 60, F0 The register designated by N (i.e., R(N)) points to memory for the “load D from memory” instructions 0N and 4N and the “Store D” instruction 5N. The register designated by P (i.e.,the program counter) is used as the data pointer for ALU instructions F8 - FD, FF, 7C, 7D, 7F. During these instruction Designates which register is Program Counter executions, the operation is referred to as “data immediate”.
Designates which register is Data Pointer Another important use of R as a data pointer supports the built-in Direct-Memory-Access (DMA) function. When a DMA-ln or DMA-Out request is received, one machine cycle Holds old X, P after Interrupt (X is high nibble) is “stolen”. This operation occurs at the end of the executemachine cycle in the current instruction. Register R(0) is always used as the data pointer during the DMA operation.
The data is read from (DMA-Out) or written into (DMA-ln) thememory location pointed to by the R(0) register. At the end CDP1802 Control Modes
of the transfer, R(0) is incremented by one so that the pro-cessor is ready to act upon the next DMA byte transfer The WAIT and CLEAR lines provide four control modes as request. This feature in the 1800-series architecture saves a substantial amount of logic when fast exchanges of blocks of data are required, such as with magnetic discs or during Data Registers
When registers in R are used to store bytes of data, four instructions are provided which allow D to receive from orwrite into either the higher-order or lower-order byte portions The function of the modes are defined as follows: of the register designated by N. By this mechanism (together with loading by data immediate) program pointer and datapointer designations are initialized. Also, this technique Holds the CPU in the IDLE execution state and allows an I/O allows scratchpad registers in R to be used to hold general device to load the memory without the need for a “bootstrap” data. By employing increment or decrement instructions, loader. It modifies the IDLE condition so that DMA-lN opera- such registers may be used as loop counters.
tion does not force execution of the next instruction.
The Q Flip-Flop
An internal flip-flop, Q, can be set or reset by instruction and Registers l, N, Q are reset, lE is set and 0’s (VSS) are placed can be sensed by conditional branch instructions. The output on the data bus. TPA and TPB are suppressed while reset is of Q is also available as a microprocessor output.
held and the CPU is placed in S1. The first machine cycle aftertermination of reset is an initialization cycle which requires 9clock pulses. During this cycle the CPU remains in S1 and reg-ister X, P, and R(0) are reset. Interrupt and DMA servicing are CDP1802A, CDP1802AC, CDP1802BC
suppressed during the initialization cycle. The next cycle is an Run-Mode State Transitions
S0, S1, or an S2 but never an S3. With the use of a 71 instruc- The CPU state transitions when in the RUN and RESET tion followed by 00 at memory locations 0000 and 0001, this modes are shown in Figure 25. Each machine cycle requires feature may be used to reset IE, so as to preclude interrupts the same period of time, 8 clock pulses, except the initializa- until ready for them. Power-up reset can be realized by con- tion cycle, which requires 9 clock pulses. The execution of necting an RC network directly to the CLEAR pin, since it has a an instruction requires either two or three machine cycles, Schmitt triggered input, see Figure 24.
S0 followed by a single S1 cycle or two S1 cycles. S2 is the response to a DMA request and S3 is the interrupt response.
Table 2 shows the conditions on Data Bus and Memory Address lines during all machine states.
THE RC TIME CONSTANT
SHOULD BE GREATER THAN
THE OSCILLATOR START-UP
Instruction Set
TIME (TYPICALLY 20ms)
The CPU instruction summary is given in Table 1. Hexadeci-mal notation is used to refer to the 4-bit binary codes.
FIGURE 24. RESET DIAGRAM
In all registers bits are numbered from the least significantbit (LSB) to the most significant bit (MSB) starting with 0.
Stops the internal CPU timing generator on the first negative high-to-low transition of the input clock. The oscillator contin-ues to operate, but subsequent clock transitions are ignored.
May be initiated from the Pause or Reset mode functions. If initiated from Pause, the CPU resumes operation on the first negative high-to-low transition of the input clock. When initi-ated from the Reset operation, the first machine cycle follow- This notation means: The memory byte pointed to by R(N) is ing Reset is always the initialization cycle. The initialization loaded into D, and R(N) is incremented by 1.
cycle is then followed by a DMA (S2) cycle or fetch (S0) fromlocation 0000 in memory.
IDLE • DMA • INT
(LONG BRANCH,
LONG SKIP, NOP, ETC.)
S1 EXECUTE
INT • DMA
DMA • IDLE • INT
DMA • INT
PRIORITY: FORCE S0, S1
INT • DMA
DMA IN
DMA OUT
INT
FIGURE 25. STATE TRANSITION DIAGRAM
CDP1802A, CDP1802AC, CDP1802BC
TABLE 1. INSTRUCTION SUMMARY (SEE NOTES)
INSTRUCTION
MNEMONIC
OPERATION
MEMORY REFERENCE
REGISTER OPERATIONS
LOGIC OPERATIONS (Note 1)
SHIFT D RIGHT, LSB(D) → DF, 0 → MSB(D) SHIFT D RIGHT, LSB(D) → DF, DF → MSB(D) SHIFT D RIGHT, LSB(D) → DF, DF → MSB(D) SHIFT D LEFT, MSB(D) → DF, 0 → LSB(D) SHIFT D LEFT, MSB(D) → DF, DF → LSB(D) SHIFT D LEFT, MSB(D) → DF, DF → LSB(D) ARITHMETIC OPERATIONS (Note 1)
M(R(P)) + D + DF → DF, D; R(P) + 1 → R(P) CDP1802A, CDP1802AC, CDP1802BC
TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued)
INSTRUCTION
MNEMONIC
OPERATION
M(R(P)) - D - (Not DF) → DF, D; R(P) + 1 → R(P) D-M(R(P))-(NOT DF) → DF, D; R(P) + 1 → R(P) BRANCH INSTRUCTIONS - SHORT BRANCH
IF D = 0, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) IF D NOT 0, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) IF DF = 1, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) IF DF = 0, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) IF Q = 1, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) IF Q = 0, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) IF EF1 =1, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) IF EF1 = 0, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) IF EF2 = 1, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) IF EF2 = 0, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) IF EF3 = 1, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) IF EF3 = 0, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) IF EF4 = 1, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) IF EF4 = 0, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) BRANCH INSTRUCTIONS - LONG BRANCH
M(R(P)) → R(P). 1, M(R(P) + 1) → R(P).0 lF D = 0, M(R(P)) → R(P).1, M(R(P) +1) → R(P).0,ELSE R(P) + 2 → R(P) IF D Not 0, M(R(P)) → R(P).1, M(R(P) + 1) → R(P).0, ELSE lF DF = 1, M(R(P)) → R(P).1, M(R(P) + 1) → R(P).0, ELSER(P) + 2 → R(P) IF DF = 0, M(R(P)) → R(P).1, M(R(P) + 1) → R(P).0, ELSER(P) + 2 → R(P) IF Q = 1, M(R(P)) → R(P).1, M(R(P) + 1) → R(P).0,ELSE R(P) + 2 → R(P) CDP1802A, CDP1802AC, CDP1802BC
TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued)
INSTRUCTION
MNEMONIC
OPERATION
lF Q = 0, M(R(P)) → R(P).1, M(R(P) + 1) → R(P).0EISE R(P) + 2 → R(P) SKIP INSTRUCTIONS
IF D = 0, R(P) + 2 → R(P), ELSE CONTINUE IF D Not 0, R(P) + 2 → R(P), ELSE CONTINUE IF DF = 1, R(P) + 2 → R(P), ELSE CONTINUE IF DF = 0, R(P) + 2 → R(P), ELSE CONTINUE IF Q = 1, R(P) + 2 → R(P), ELSE CONTINUE IF Q = 0, R(P) + 2 → R(P), ELSE CONTINUE IF IE = 1, R(P) + 2 → R(P), ELSE CONTINUE CONTROL INSTRUCTIONS
WAIT FOR DMA OR INTERRUPT; M(R(0)) → BUS (X, P) → T; (X, P) → M(R(2)), THEN P → X; R(2) - 1 → R(2) M(R(X)) → (X, P); R(X) + 1 → R(X), 1 → lE M(R(X)) → (X, P); R(X) + 1 → R(X), 0 → lE INPUT - OUTPUT BYTE TRANSFER
M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 1 M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 2 M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 3 M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 4 M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 5 M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 6 M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 7 CDP1802A, CDP1802AC, CDP1802BC
TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued)
INSTRUCTION
MNEMONIC
OPERATION
1. The arithmetic operations and the shift instructions are the only instructions that can alter the DF.
After an add instruction:DF = 1 denotes a carry has occurredDF = 0 Denotes a carry has not occurredAfter a subtract instruction:DF = 1 denotes no borrow. D is a true positive numberDF = 0 denotes a borrow. D is two’s complementThe syntax “-(not DF)” denotes the subtraction of the borrow.
2. This instruction is associated with more than one mnemonic. Each mnemonic is individually listed.
3. An idle instruction initiates a repeating S1 cycle. The processor will continue to idle until an I/O request (INTERRUPT, DMA-lN, or DMA- OUT) is activated. When the request is acknowledged, the idle cycle is terminated and the I/O request is serviced, and then normal operation is resumed.
4. Long-Branch, Long-Skip and No Op instructions require three cycles to complete (1 fetch + 2 execute).
Long-Branch instructions are three bytes long. The first byte specifies the condition to be tested; and the second and third byte, thebranching address.
If the tested condition is met, then branching takes place; the branching address bytes are loaded in the high-and-low order bytes of thecurrent program counter, respectively. This operation effects a branch to any memory location.
If the tested condition is not met, the branching address bytes are skipped over, and the next instruction in sequence is fetched and exe-cuted. This operation is taken for the case of unconditional no branch (NLBR).
5. The short-branch instructions are two bytes long. The first byte specifies the condition to be tested, and the second specifies the branching address.
Test the status (1 or 0) of the four EF flags If the tested condition is met, then branching takes place; the branching address byte is loaded into the low-order byte position of thecurrent program counter. This effects a branch within the current 256-byte page of the memory, i.e., the page which holds the branchingaddress. If the tested condition is not met, the branching address byte is skipped over, and the next instruction in sequence is fetchedand executed. This same action is taken in the case of unconditional no branch (NBR).
6. The skip instructions are one byte long. There is one Unconditional Short-Skip (SKP) and eight Long-Skip instructions.
The Unconditional Short-Skip instruction takes 2 cycles to complete (1 fetch + 1 execute). Its action is to skip over the byte following it.
Then the next instruction in sequence is fetched and executed. This SKP instruction is identical to the unconditional no-branch instruc-tion (NBR) except that the skipped-over byte is not considered part of the program.
The Long-Skip instructions take three cycles to complete (1 fetch + 2 execute).
If the tested condition is met, then Long Skip takes place; the current program counter is incremented twice. Thus two bytes are skippedover, and the next instruction in sequence is fetched and executed. If the tested condition is not met, then no action is taken. Executionis continued by fetching the next instruction in sequence.
CDP1802A, CDP1802AC, CDP1802BC
TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES
OPERATION
CDP1802A, CDP1802AC, CDP1802BC
TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued)
OPERATION
CDP1802A, CDP1802AC, CDP1802BC
TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued)
OPERATION
1. lE = 1, TPA, TPB suppressed, state = S1.
6. IN REQUEST has priority over OUT REQUEST.
7. See Timing Waveforms, Figure 5 through Figure 14 for machine cycles.
Operating and Handling Considerations
Handling
Input Signals - To prevent damage to the input protection
circuit, input signals should never be greater than V
All inputs and outputs of Intersil CMOS devices have a net- work for electrostatic protection during handling.
SS. Input currents must not exceed 10mA even Operating
Unused Inputs - A connection must be provided at every
Operating Voltage - During operation near the maximum
input terminal. All unused input terminals must be connected supply voltage limit care should be taken to avoid or suppress to either VDD or VSS, whichever is appropriate.
power supply turn-on and turn-off transients, power supply rip- Output Short Circuits - Shorting of outputs to VDD or VSS
ple, or ground noise; any of these conditions must not cause may damage CMOS devices by exceeding the maximum VDD - VSS to exceed the absolute maximum rating.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time withoutnotice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurateand reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties whichmay result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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